`default_nettype none

module chip (
    output     [2:0] led,
    output           uart_tx,
    input            uart_rx,
    output           spi_miso,
    input            spi_mosi,
    input            spi_sck,
    input            spi_cs,
    input            ram_data1,
    output           ram_data0,
    output           ram_data2,
    output           ram_data3,
    output           ram_sck,
    output           ram_cs,
);

// PSRAM passthrough
assign spi_miso = ram_data1;
assign ram_data0 = spi_mosi;
assign ram_cs = spi_cs;
assign ram_sck = spi_sck;
assign ram_data2 = 0;
assign ram_data3 = 0;

// UART loopback
assign uart_tx = uart_rx;

// Debug on LED
assign led[0] = uart_rx; // Blue
assign led[1] = 1; // Green
assign led[2] = ~spi_mosi; // Red

endmodule